Several works were conducted to reduce the energy consumption in electrical circuits. Reversible circuits synthesis is considered one of the major efforts paid to reduce the amount of power consumption. Synthesizing reversible circuits field has a lot of proposed algorithms to minimize the overall cost of circuits synthesis (in terms of line number and quantum cost) with a minimal concern paid for synthesis time. However, because of the iterative nature of the synthesis optimization algorithms, synthesis time cannot be neglected as a parameter to be tackled, especially for large scale circuits to be realized by cascades of reversible gates. Reducing synthesis cost can be achieved by Binary Decision Diagrams (BDDs) that are considered a step forward in this field. Nevertheless, mapping each BDD node into a cascade of reversible gates during the synthesis process is time-consuming. In this work, we are implementing the idea of subtree-based mapping of BDD nodes to reversible gates instead of the classical nodal-based algorithm to effectively reduce the entire reversible circuits synthesis time. Considering Depth First Search (DFS), we are converting a whole BDD subtree in one step into a cascade of reversible gates. All possible subtrees combinations are previously saved in a two-column lookup table of subtrees and their corresponding reversible gates. This table is constructed as a result of a comprehensive study of all possible BDD subtrees and considered as a reference during the conversion process. The conducted experimental tests show a significant synthesis time reduction (around 95\% on average) with preserving the correctness of the algorithm in generating a circuit realizing the required Boolean function.

Title

Applied Science

Publisher

MDPI

Publisher Country

Switzerland

Indexing

Scopus

Impact Factor

2.217

Publication Type

Online only

Volume

10

Year

2020

Pages

17